As is well known in the art, integrated circuit memories are generally tested to a large degree by operating the memory in its normal operating mode, in which each operating cycle writes data to or reads data from a single addressable location. Because of the high cost of modern automated test equipment, however, it is highly desirable to reduce the time required for testing each individual integrated circuit, to maximize throughput through and utilization of costly test equipment.
Many modern integrated circuits, particularly semiconductor memories, utilize special test modes in which elements within the memory may be tested or stressed in an efficient or improved manner relative to test patterns performed in normal operating mode. By way of background, it is known in the art to enable the selection of a special test mode, as opposed to a normal operating mode, by applying one or more so-called "overvoltage" signals (i.e., out of the specification range for normal operation) to one or more terminals of the integrated memory circuit, often in conjunction with a code to select one of several available test modes. Examples of techniques for entering special test mode are described in U.S. Pat. No. 5,072,138, issued Dec. 10, 1991, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference. Examples of such special test modes include "parallel" read and write operations, in which more memory cells than those associated with a single addressable location are accessed in a single memory cycle; such parallel reads and writes thus reduce the number of memory cycles required to exercise the entire memory. In addition, as described in my copending application Ser. No. 08/173,197, filed Dec. 22, 1993, assigned to SGS-Thomson Microelectronics, Inc. and incorporated herein by this reference, special tests may also be used to screen functional failures that would only be found in extremely long functional tests in normal operating mode, such as long cycle time reads or writes.
Another type of conventional special test operation stresses certain internal nodes of the memory with voltages beyond those encountered during normal operation. These special stress tests accelerate time and voltage dependent transistor failure mechanisms, (e.g., MOSFET gate dielectric failure). As a result, failure mechanisms that may only become apparent over time may be screened during manufacturing testing.
By way of further background, my copending U.S. application Ser. No. 08/172,854, filed Dec. 22, 1993, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference, describes certain stress tests, performable in a special test mode, for screening integrated memory circuits for latent reliability failures. As described in this copending U.S. application 08/172,854, a memory of the type having differential bit lines associated with each column of memory cells may be stressed, in a special test mode, by maintaining one of the bit lines of the pair at a high voltage (e.g., an elevated V.sub.cc voltage of on the order of 9 volts, where V.sub.cc in normal operation is nominally 5 volts), while maintaining the other bit line at ground. This stress test described in copending U.S. application Ser. No. 08/172,854, as well as other stress tests performed in a special test mode, is preferably performed by ramping the elevated power supply voltage to the stress level after the device has already been placed in the special test mode. This procedure is preferable, as large switching transients are avoided.
For all types of special stress tests, however, it is important to ensure that the high stress voltages applied internally to the integrated memory circuit in such a special stress test mode do not cause damage to the circuit that would otherwise not occur. This concern is also present, to some extent, for special test operations not involving the application of stress voltages, as the particular test conditions in a special test mode may be sufficiently different from normal operation as to present certain failure risks.
It is therefore an object of the present invention to provide a method and circuit for protecting integrated circuits from damage during special test modes, particularly those utilizing stress voltages.
It is a further object of the present invention to improve the reliability of integrated memory circuits by enabling the safe performance of stress tests therewithin.
It is a further object of the present invention to lock-out certain operating circuitry from affecting the operation of an integrated memory circuit while high stress voltages are applied thereto.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification, together with the claims.